(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to form via holes.
(2) Description of Prior Art
The major objectives of the semiconductor industry has been to continually increase the device and circuit performance of silicon chips, while maintaining, or even decreasing, the cost of producing these same silicon chips. These objectives have been successfully addressed by the ability of the semiconductor industry to fabricate silicon devices, with sub-micron features. The ability to use sub-micron features, or micro-miniaturazation, has allowed performance improvements to be realized by the reduction of resistances and parasitic capacitances, resulting from the use of smaller features. In addition, the use of sub-micron features, results in smaller silicon chips with increased circuit densities, thus allowing more silicon chips to be obtained from a starting silicon substrate, thus reducing the cost of an individual silicon chip.
The attainment of micro-miniaturazation has been basically a result of advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching. The development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron features in photoresist layers to be routinely achieved. In addition similar developments in the dry etching discipline, has allowed these sub-micron images in photoresist layers, to be successfully transferred to underlying materials, used for the creation advanced semiconductor devices. However the use of sub-micron features, although improving silicon device performance and decreasing silicon chip cost, introduces specific semiconductor fabrication problems, not encountered with larger featured counterparts. For example, specific designs sometimes require that metal filled via holes, in insulator layers, used to connect an overlying metallization structure to an underlying metallization structure, not always be fully landed. That is the metal filled via, not being placed entirely on the underlying metallization structure. The inability to fully land a via on an underlying metal structure, places a burden on the process used to create the via hole. For example if the chip design demands a non-fully landed, or a borderless contact, the dry etching procedure, used to create the via, has to be able to insure complete removal of insulator material from the area where the via landed on the underlying metal structure, therefore necessitating the use of an overetch cycle. The overetch cycle however, can create problems in the area where the via missed the underlying metal structure, and resided partially on an underlying insulator layer. The underlying insulator layer, may be identical, or similar, to the insulator used for the via formation. The extent of the via hole overetch cycle can then result in severe etching of the underlying insulator layer, to a point where a lower level metallization structure may be exposed. Subsequent metal filling of the via hole can then result in interlevel leakages or shorts. In addition the above phenomena can even occur, due to photolithographic misalignment situations, with fully landed contacts.
Shibata, et al, in U.S. Pat. No. 5,350,712 describe a process for alleviating the consequences of the via hole misalignment, or borderless contact phenomena. However this present invention will describe a different approach to the misalignment or borderless contact, via hole phenomena. An approach which offers protection from misalignment problems, with little added cost or complexity.